# Enclavia Neuromorphic Space Edge Intelligence Whitepaper

> Source: /resources/whitepapers/Enclavia%20Neuromorphic%20Space%20Edge%20Intelligence%20Whitepaper.pdf

## Models for Distributed Space-Based Edge

Intelligence A build-or-wait assessment for developers and solution engineers: what runs on real silicon today, what survives the radiation environment, what the energy numbers actually mean, and where the reference architecture should draw its lines.

## FIELD DETAIL

Audience Deep tech developers, solution engineers, ML systems engineers, space systems architects, mission software leads Document type Technical assessment with sourcing ledger. Not a product datasheet. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 1 of 36

## FIELD DETAIL

Version / date 1.0 · 31 July 2026 Author Dev Roy, Founder & CEO, Enclavia.ai · Enterprise Architect, AI Platform Architect Sourcing standard Every load-bearing number is tier-labelled. Claims that failed primary-source verification are named and excluded, not softened.

Reading time Approximately 45 minutes. Sections 2 through 4 carry the engineering substance; Section 9 carries the decision. dev@enclavia.ai · 703-984-9981 · enclavia.ai · Fairfax, Virginia Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 2 of 36 Contents

## SECTION WHAT IT CONTAINS

1 · Executive Summary Three findings that should change a design decision, and the staged recommendation they support.

## Sourcing Standard and Evidence

Ledger The four-tier labelling scheme, three corrections to figures in common circulation, and the contradictions between sources left visible.

## Neuromorphic Fundamentals for the

Practitioner Where the energy actually goes, neuron model selection, the silicon comparison with measurement conditions attached, and what NeuroBench fixed.

## Spiking and Event-Driven Language

Models What exists, why autoregressive decoding resists neuromorphic hardware, conversion versus direct training, and the deployable ternary alternative.

## Radiation Tolerance and the Space

Environment Effect taxonomy, dose by orbit regime, what is actually known about neuromorphic parts under radiation, and the asymmetry of spiking fault tolerance. 6 · Use Case Deep Dives On-board intelligence, LEO user terminals, autonomous swarms, intermittent-power operation, deep-space autonomy, and defence applications.

7 · Reference Architecture for Builders The node architecture, spike encoding selection, toolchain reality check, flight interfaces, and the assurance gap. 8 · Economics and Mission Trade-offs Downlink economics, the compute-in-orbit break-even, power-to-mass-to-dollars, and orbital data centres.

9 · Limitations and Honest Assessment Where the argument fails, the overpromising risk, and four falsifiable conditions that would change the assessment.

## What to Build, What to Pilot, What to

## Leave Alone

The three-stage adoption model and the promotion signals for each stage. Appendix A · Evidence Ledger Every load-bearing claim sorted by tier, including the four claims excluded for lack of a primary source. Appendix B · Primary Sources Full citation list across neuromorphic computing, spiking language models, radiation effects, space missions and economics.

Index of Exhibits

## EXHIBIT TITLE SECTION Energy efficiency: claimed versus defensible 3.3

## Radiation environment by orbit regime 5.1

## The bits-to-decisions problem 6.1

## Why the hybrid architecture wins on power 6.4

## Reference architecture: space-based event-driven inference node 7

## Technology readiness: what is actually flyable 6.6

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 3 of 36

## EXHIBIT TITLE SECTION Spiking fault tolerance is real, and it is asymmetric 5.3

## The spiking LLM landscape: scale versus deployability 4.1

## Neuromorphic silicon: power envelope versus flight reality 3.3

## Light-time delay is why on-board autonomy is not optional 6.5

## What to build, what to pilot, what to leave alone 10

## Evidence ledger for this document 2

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 4 of 36

- Executive Summary

The short version: event-driven neuromorphic hardware is real and flight-proven at the sensor and small-accelerator scale. Neuromorphic large language models are not. Those two facts are usually collapsed into one claim in vendor material, and collapsing them is how space programmes end up budgeting for a capability that has no on-chip demonstration at any parameter scale.

I have spent twenty years architecting platforms for federal agencies and Fortune 500 programmes, and the pattern in this field is one I recognise. A genuine physical advantage at the device level gets extrapolated into a system-level promise that the toolchain, the radiation data, and the certification path cannot yet support. This paper separates the two so an engineering team can act on the first without betting a mission on the second.

### Three findings that should change a design decision

## FINDING 1 — THE EFFICIENCY ADVANTAGE IS REAL, AND IT IS NOT 1000×

The defensible, independently benchmarked range for spiking inference on real silicon against edge-class baselines is roughly 10× to 250×, and it is task-dependent. Mészáros et al. (arXiv:2510.13757, October 2025) state that classification on Intel Loihi 2 is up to 18× faster and uses 250× less energy than the same task on an NVIDIA Jetson Orin Nano. That is one narrow keyword-spotting workload, batch size 1, on the Spiking Heidelberg Digits dataset, against one specific 8 GB / 15 W Jetson configuration.

Numbers above roughly 1000× almost always compare against a non-edge baseline, or count only synaptic-operation energy while ignoring I/O, memory traffic and static draw. The 99% energy reduction figure quoted for BrainChip Akida benchmarks against a desktop RTX 3090, which is not an edge-class part.

## FINDING 2 — THE STRONGEST NEAR-TERM SPACE CASE IS DATA TRIAGE, NOT LANGUAGE

ESA's Phi-sat-1, running the CloudScout CNN on an Intel Myriad 2 VPU, achieved roughly a 90% reduction in downlink data volume at about 92% accuracy, 325 ms inference and 2 W per inference. Event cameras on the ISS have survived roughly three years in low Earth orbit with minimal radiation degradation.

For this workload the deployable choice in 2026 is a quantised CNN on a COTS VPU or FPGA, or a small SNN on BrainChip Akida. It is not a neuromorphic language model.

## FINDING 3 — BUILD HYBRID, AND USE TERNARY QUANTISATION FOR THE LANGUAGE STEP

The architecture that survives contact with a real power budget is an event-driven always-on front-end gating a conventional, quantised reasoning core. A 1 W front-end gating a 10 W reasoner at a 1% duty cycle draws 1.1 W orbit-average, an 89% reduction against continuous operation, with no loss of event coverage.

For the language layer, BitNet b1.58 ternary models are released, run on conventional CPUs and edge silicon today, and require no neuromorphic hardware at all. Ma et al. (arXiv:2402.17764) report that ternary weights match full-precision LLaMA perplexity at 3B parameters while running 2.71× faster and using 3.55× less GPU memory; at 70B, matrix multiplication is 71.4× more energy-efficient.

### The decision this paper supports

If you are scoping a space-based edge intelligence programme in 2026, the recommendation is staged. Build on-board triage now with proven parts. Pilot neuromorphic silicon against your own workload with your own Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 5 of 36 benchmarks. Watch the spiking language model literature, but do not put it on a critical path. Exhibit 11 sets out the three stages and the specific signals that would justify promoting an item from one stage to the next.

What follows is the evidence for that position, including the four claims a reader might reasonably expect to find in a document like this that have been deliberately left out because no primary source supports them. Those exclusions are listed in Section 10 and in Exhibit 12.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 6 of 36

- Sourcing Standard and Evidence Ledger

This field has a citation hygiene problem. The same efficiency ratio gets repeated across a dozen articles until its original baseline is lost, and by the time it reaches a programme office it has become a specification. Every quantitative claim in this document therefore carries a tier label, and the tiers are applied consistently.

## TIER DEFINITION HOW IT MAY BE USED

T1 Independently benchmarked, peer-reviewed, or validated in flight. The measurement conditions are stated in the source. Usable as a planning figure, provided the workload and baseline are carried forward with the number.

T2 Vendor-stated or press-reported. Plausible, but the measurement conditions are controlled by the party making the claim. Usable for directional sizing. Not usable in a requirements document without independent confirmation.

T3 Forecast, projection, or conditional claim. Includes figures that depend on hardware the authors did not measure on. Usable only as a hypothesis. Never usable as a design input. EX Could not be verified from a primary source. Named and excluded.

Not asserted anywhere in this document. Exhibit 12. Distribution of load-bearing quantitative claims in this document by evidence tier. The right-hand column is the important one: four numbers a reader might expect to find here were removed rather than caveated.

### Corrections to figures in common circulation

Three numbers that circulate widely in this domain do not survive checking, and are corrected here rather than repeated. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 7 of 36

- The "1000× energy efficiency" figure. No apples-to-apples benchmark supports it. The best independently

measured result available is 250× on a single narrow task against a named edge baseline. NeuroBench, published in Nature Communications in 2025 with contributions from more than 100 researchers across 50-plus institutions, exists specifically because cross-architecture comparisons in this field have historically been mismatched.

- The 23.6 pJ per synaptic operation figure attributed to Loihi 2. That value is from Davies et al. (2018) and

describes Loihi 1. It should not be carried forward to Loihi 2, which is a different process node and a different architecture. No Loihi-2-specific picojoule-per-synaptic-operation figure was verifiable from a primary source.

- Radiation tolerance claims that conflate TID with single-event effects. Total ionising dose and single-event

effects are separate failure axes with separate mitigations. A part can be TID-tolerant and latch-up fatal, or the reverse. Section 4 treats them separately throughout.

### Contradictions between sources, left visible

Where reputable sources disagree, this document says so rather than picking the more favourable number.

## CLAIM THE DISAGREEMENT POSITION TAKEN HERE

Intel Hala Point throughput Cited as both 20 petaops and 30 petaops across outlets. Intel's own release states 20 petaops. That figure is used. Hala Point inter-core bandwidth Cited as 3.5 PB/s and as 11 PB/s. Not used as a load-bearing figure anywhere in this document.

AEGIS autonomous targeting success Reported as both >93% and >86% depending on metric and period. The Science Robotics figure (>93%, against a ~24% no-intelligence baseline) is used, with its baseline stated. SpikeGPT "5× less energy" Presented in secondary coverage as a measured result.

It is conditional on neuromorphic hardware able to exploit the model's sparsity, and was not measured on such hardware. Labelled T3. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 8 of 36

- Neuromorphic Fundamentals for the Practitioner

This section assumes you can write CUDA but have not shipped a spiking network. It covers only what changes a design decision.

### Where the energy actually goes

Spiking neural networks communicate through binary events. On Loihi 2 the events can carry a graded integer payload up to 24 bits, but the principle holds: a neuron consumes energy only when it receives a spike. That gives activity-dependent dynamic power and no idle dynamic draw, which is the first lever.

The second lever is arithmetic. Because a spiking neuron accumulates weights rather than multiplying and accumulating them, the multiply unit disappears from the inner loop. The third and largest lever is memory locality. In conventional inference, data movement can account for up to 90% of total energy. Neuromorphic architectures co-locate memory with compute per core, which attacks that term directly rather than optimising around it.

Sparsity ties the three together. The ESA and Politecnico di Milano study (Lunghi et al., arXiv:2505.11418, 2025) confirms that energy on these parts scales with spike count and synaptic operations, not with wall-clock time. A network that fires rarely is cheap in a way that a quantised dense network is not, and a network that fires constantly forfeits most of the advantage.

## PRACTICAL CONSEQUENCE

If your input is dense and your activations are dense, neuromorphic silicon will not save you much. The advantage is a function of the sparsity of your problem, not of the hardware alone. Event cameras, sparse RF, and change-detection workloads are natural fits. Full-frame dense imagery at high duty cycle is not.

### Neuron models, and which one to pick

## MODEL BEHAVIOUR COST WHEN TO USE

## (LIF)

Membrane potential integrates input and decays; fires at threshold. Lowest The default. Used by SpikeGPT and by most deployed hardware. Start here. Non-leaky integrate-and-fire (IF) As LIF without the decay term. Lowest Where the leak adds nothing. The ESA study used LIF and IF specifically to minimise computation.

Adaptive LIF Adds spike-frequency adaptation. Moderat e Where you need the network to habituate to a persistent stimulus. Izhikevich Richer biological dynamics, bursting and chattering regimes. Highest Rarely justified in an energy-constrained deployment. Research use.

### The silicon, with its measurement conditions attached

The table below is the honest version. Each figure carries the baseline it was measured against, because without that context none of these numbers are comparable to each other. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 9 of 36

## PLATFORM PROCESS KEY REPORTED FIGURE TIER

## Intel Loihi 2 Intel 4 (7 nm

class) Up to 250× less energy and 18× faster than an NVIDIA Jetson Orin Nano on keyword spotting (Spiking Heidelberg Digits, batch size 1). The 23.6 pJ per synaptic operation figure often quoted alongside is a Loihi 1 number.

T1 Intel Hala Point Intel 4 1,152 Loihi 2 chips. 1.15 billion neurons, 128 billion synapses, 140,544 cores, 2,600 W or less. Greater than 15 TOPS/W on 8-bit DNN. 20 petaops. Claimed 100× less energy and 50× faster than CPU/GPU on selected workloads.

T2 IBM NorthPole 12 nm 25× more frames per joule than a 12 nm GPU on ResNet-50. Roughly 4,000× faster than TrueNorth. Sub-millisecond per-token latency on a 3B model, reported 70× more energy-efficient than the next-lowest-latency GPU.

T1 / T2 IBM TrueNorth 28 nm 4,096 cores, 1 million neurons, 256 million synapses, 65 mW in real-time operation, 400 GSOPS/W. T1

## BrainChip Akida AKD1000

## nm 80 NPUs, roughly 1.2 million neurons, 10 billion synapses. About 1 W on the M.2 form

factor. Roughly 45 μJ per inference on a robotics task; 1.7 mJ per image and a 99% energy reduction on a skin-disease SNN — measured against a desktop RTX 3090, not an edge part. T1 Innatera Pulsar (T1) Not disclosed Sub-milliwatt to microwatt operation. 600 μW radar presence detection, 400 μW audio scene classification. Vendor claims 500× lower energy and 100× lower latency than a conventional AI microcontroller.

T2 SpiNNaker2 22 nm FDSOI ARM-core digital neuromorphic architecture. Not deeply benchmarked in the sources reviewed for this document. — Exhibit 1. Reported efficiency advantages, each against its own stated baseline. The bars are deliberately not normalised, because normalising them would imply a comparability that does not exist.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 10 of 36 Exhibit 9. Operating power envelope plotted against flight availability. The inversion visible here is the central procurement problem in this domain: the parts with the strongest efficiency figures have the least space heritage, and the only part in the set with an operational on-orbit inference result is not a spiking processor at all.

### The benchmarking problem, and what NeuroBench fixed

Until recently there was no accepted way to compare a spiking implementation against a conventional one. Vendors chose their own baselines, their own batch sizes and their own workloads, and the resulting ratios ranged over three orders of magnitude for what was nominally the same claim.

NeuroBench addresses this with a two-track framework: a hardware-independent algorithm track and a hardware-dependent system track. For an engineering team the operational advice is direct. Do not accept a vendor ratio for your workload. Run the NeuroBench system track on your own data, on the part you are actually considering, against the edge baseline you would otherwise ship. Every number in Exhibit 1 was produced under conditions that differ from yours.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 11 of 36

- Spiking and Event-Driven Language Models: State of the Art

This is the section where the field's marketing and the field's engineering diverge most sharply. The distinction that matters is not model size. It is whether the model has ever executed on neuromorphic silicon.

### What exists

## MODEL SCALE WHAT IT ACTUALLY DEMONSTRATES TIER

SpikeGPT (Zhu et al., arXiv:2302.13939) 45M / 125M / 260M parameters The largest functional spiking language model at publication. Replaces multi-head self-attention with a recurrent linear-attention block (Spiking RWKV) to achieve linear complexity in sequence length. Uses LIF neurons, rate coding and surrogate-gradient training. Reports roughly 5× less energy when processed on neuromorphic hardware able to leverage sparse event-driven activations — a conditional claim, not an on-chip measurement.

T3 SpikeLLM (Xing et al., arXiv:2407.04752, ICLR 2025) 7B to 70B parameters Scales spiking mechanisms, not a spiking deployment. Uses Generalized Integrate-and-Fire neurons and an Optimal Brain Spiking framework. On LLaMA-7B at W4A4 it reduces WikiText2 perplexity by 11.01% and improves reasoning accuracy by 2.55% against OmniQuant. Evaluated on GPUs and framed as competitive with quantisation.

T1 Meta-SpikeFormer / Spike-driven

## Transformer V2 (ICLR

2024) 55M parameters First SNN backbone to reach 80.0% top-1 on ImageNet-1K, supporting classification, detection and segmentation. T1 Spike-driven

## Transformer V3 (T-PAMI

2025) 173M parameters 86.2% top-1 on ImageNet-1K. T1 Spike-driven

## Transformer (NeurIPS

- Spike-driven self-attention using only masking and addition. Claims up to 87.2×

lower attention-computation energy than vanilla self-attention. T1

## QSD-Transformer (ICLR

2025) 6.8M parameters 80.3% top-1 at 8.7 mJ. The strongest accuracy-per-parameter result in the set. T1 NSLLM on VCK190 FPGA 1.5B parameters 13.849 W dynamic power, 161.8 tokens per second, with 19.8× energy efficiency, 21.3× memory and 2.2× throughput improvements against an A800 GPU. This is a MatMul-free FPGA core, not a neuromorphic chip, and it is the closest thing to a spiking language model running off a GPU.

T1 Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 12 of 36 Exhibit 8. Model scale against deployment reality. Everything above one billion parameters in the spiking column executes on a GPU. The column that runs on real neuromorphic silicon tops out in the low millions of parameters.

### Why autoregressive decoding resists neuromorphic hardware

This is worth understanding precisely, because it explains why the gap in Exhibit 8 is structural rather than a matter of engineering effort.

- Attention needs global routing. Every token attends to every other token, which requires content-based routing

across the whole sequence. Neuromorphic substrates are locally connected, event-routed meshes. The communication pattern is the wrong shape.

- The KV-cache is hostile to the memory model. It is a large, growing, randomly accessed state store.

Neuromorphic cores use small per-core SRAM precisely to keep memory next to compute. The two designs pull in opposite directions.

- Membrane potential is itself a memory cost. State must be held per neuron per timestep, and that cost grows

with the number of timesteps you need for accuracy. This is why the successful work either linearises attention, as SpikeGPT does, or keeps the matrix multiplication on conventional units, as SpikeLLM does. Neither approach puts a transformer decoder on a neuromorphic mesh, and no published work does.

### Conversion versus direct training

## APPROACH MECHANISM TRADE-OFF

ANN-to-SNN conversion (rate-based) Train a conventional network, then map activations to firing rates. Simple and reuses existing training pipelines, but needs many timesteps to converge. That raises latency and frequently erodes the energy advantage on complex data.

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## APPROACH MECHANISM TRADE-OFF

Direct training with surrogate gradients (STBP, SuperSpike,

## SLAYER)

Train the spiking network directly, substituting a differentiable surrogate for the non-differentiable spike. Better accuracy and energy at low timestep counts, but memory-hungry because of backpropagation through time, and difficult to scale to deep networks.

Sigma-delta / graded-spike conversion Encode changes rather than absolute values, exploiting Loihi 2's graded spikes. Brehove et al. (arXiv:2505.06417) achieved roughly 6% of the equivalent ANN's synaptic operations on YOLO-KP. Currently the most promising conversion route for vision on Loihi 2.

### The deployable alternative: extreme quantisation

If the requirement is low-power language reasoning on a spacecraft in 2026, the answer is not a spiking model. It is a ternary one.

## BITNET B1.58 — WHY THIS IS THE RECOMMENDED LANGUAGE PATH

Ma et al. (arXiv:2402.17764) report that ternary weights drawn from {-1, 0, +1} — 1.58 bits per weight — begin to match full-precision LLaMA perplexity at 3B parameters while running 2.71× faster and using 3.55× less GPU memory. At 70B parameters, throughput is 8.9× higher and matrix multiplication is 71.4× more energy-efficient.

A 2B-parameter open model, bitnet-b1.58-2B-4T, is released and runs on conventional CPUs and edge silicon today. It requires no neuromorphic hardware, no surrogate-gradient training, no vendor-specific SDK, and no new certification argument. For a flight programme with a 2026 or 2027 delivery date, this is the path that closes.

The engineering symmetry is worth naming: extreme quantisation and event-driven computation are attacking the same two energy terms — arithmetic width and memory traffic — from opposite directions. One is deployable now on parts you can buy. The other is a research programme.

### Runs today versus runs in simulation

## STATUS WHAT IS IN THIS CATEGORY

Runs on real neuromorphic silicon today Small to mid-sized SNNs for keyword spotting, vision classification and event-camera processing. Loihi 2, BrainChip Akida, SynSense Speck and Xylo, Innatera Pulsar. Runs on FPGA NSLLM at 1.5B parameters on a VCK190. A MatMul-free core, not neuromorphic silicon.

Simulation and GPU only Every spiking language model without exception: SpikeGPT, SpikeLLM, SpikingBERT,

## SpikeBERT, Spikformer, the Spike-driven Transformer family, SpikingResformer. These

demonstrate algorithms, not chip deployment. Does not exist Any billion-parameter spiking network demonstrated on neuromorphic silicon. Any neuromorphic language model operating in orbit. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 14 of 36

- Radiation Tolerance and the Space Environment

Radiation is where a promising ground demonstration meets its first hard constraint, and where the published evidence for neuromorphic parts is thinnest. This section states what is known, what is not, and what should not be assumed.

### Taxonomy, stated separately because the failure modes are separate

## EFFECT MECHANISM MANIFESTATION MITIGATION

Total ionising dose (TID) Cumulative charge trapping in oxides. Threshold voltage shift, increasing leakage current, eventual functional failure. Process selection, shielding mass, derating, end-of-life margin. Single-event upset (SEU) Single ionising particle flips a stored bit.

Corrupted weight, corrupted state, silent wrong answer. ECC on weight memory, memory scrubbing, TMR on the decision path. Single-event transient

## (SET)

Particle-induced voltage glitch in combinational logic. Momentary wrong value that may or may not be latched. Temporal filtering, redundant sampling. Single-event functional interrupt (SEFI) Upset in control or configuration logic.

Device stops responding correctly until reset. Watchdog, configuration scrubbing, autonomous reset. Single-event latch-up

## (SEL)

Parasitic thyristor triggers a high-current state. Destructive unless current is removed fast enough. Current-limiting, latch-up protection circuits, SEL-immune process. Displacement damage Lattice damage from non-ionising energy loss.

Degraded optoelectronic and sensor performance. Part selection, particularly for imagers and optocouplers. Exhibit 2. Approximate total ionising dose by orbit regime, behind modest shielding. Four orders of magnitude separate a benign low-inclination LEO demonstrator from the GPS belt. Orbit selection dominates the parts decision more than any other single variable.

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## ORBIT DOMINANT SOURCES TYPICAL TID RATE REFERENCE POINT

LEO below 800 km, low inclination Inner-belt protons and electrons, South Atlantic Anomaly Roughly 0.01 to a few krad(Si) per year Galassia at 550 km: 0.023 krad/yr LEO polar As above, plus polar horns and cusps Up to about 2× the low-inclination rate at the same altitude — ISS orbit (~420 km) As LEO low-inclination About 0.3 nGy/s, roughly 3× sea level Falcon Neuro operated behind approximately 0.25 inch of aluminium MEO (~20,000 km, GPS belt) Outer electron belt Above 200 krad(Si) per year behind 3 mm Al The harshest regime. Difficult to meet with COTS parts.

GEO Outer-belt electrons plus solar protons Tens of krad per year; design practice around 50 krad/yr, above 1 Mrad over

## years

Electron-dominated, so dose falls quickly with added shielding Cislunar and deep space Galactic cosmic rays plus solar particle events Highly event-driven; dominated by SPEs WMAP at L2 accumulated about

### krad over 27 months What is actually known about neuromorphic parts in radiation

Very little, and it is important to say so plainly.

## PART / SYSTEM EVIDENCE STATUS

Intel Loihi — ground test Scrofano, Davis and Taggart (The Aerospace Corporation), 2024

## IEEE Space Computing Conference, pp. 86–92. Proton SEE and

TID testing. The first dedicated published radiation-test paper on the part. Specific krad and cross-section values are behind an IEEE paywall and could not be read from a primary source. Excluded from this document. Intel Loihi 1 — on orbit NASA Ames BrainStack / TechEdSat-13 (Murbach et al.,

## SSC23-X-03, NTRS 20230011460). Launched 13 January 2022 to

roughly 500 km at 45° with only about 2 mm of aluminium shielding. First neuromorphic processor in space. No significant single-event effects noted as of August 2023. Qualitative only. No published on-orbit TID or SEE figures. Notable non-radiation finding: thermal self-shutdown on runs beyond about 220 minutes, and improper operation below roughly 15 °C.

BrainChip Akida No peer-reviewed quantitative TID or SEE test data exists publicly. Only vendor and partnership statements, including Frontgrade Gaisler licensing Akida IP into the rad-hard GR801 / GRAIN SoC (December 2024).

A genuine literature gap. Akida must not be presented as radiation-qualified on current public evidence. Event camera (DAVIS

## 240C) — Falcon Neuro

## Wilcox et al., Sensors 25(21):6599, 2025 (DOI

10.3390/s25216599). Two sensors installed on the Columbus

## module on 11 January 2022. Across January 2022 to September

2024, of 18 degradation measures tracked, only one showed a convincing deterioration trend at 99% confidence. No SEL or single-event burnout observed. Radiation manifested mainly as SEU-induced hot-pixel bit-flips whose counts stayed constant.

No accumulated TID figure is given. The authors conclude a high aptitude for surviving long-duration spaceflight.

## nm FD-SOI (proxy

technology) Heavy-ion and Co-60 studies show very low SEE sensitivity. Ring-oscillator frequency degraded about 10% under heavy ion and 40% under Co-60 after 1000 krad(Si), with logic still functional. SRAM SEU cross-section around 2×10⁻¹⁰ cm² per bit at LET 15 MeV·cm²/mg without TMR.

Useful as a technology-class proxy only. Loihi 1 is

## nm FinFET, not FD-SOI. Akida is 28 nm but its

FD-SOI status is not publicly confirmed. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 16 of 36

### Inherent fault tolerance: real, bounded, and asymmetric

The argument that spiking networks degrade gracefully under fault is frequently made and is partly true. The distributed representation does absorb silent failures. What it does not absorb is a neuron stuck high. Exhibit 7. Fault tolerance in spiking networks is asymmetric. Curves are illustrative reconstructions of reported qualitative behaviour, anchored to published inflection points. Cite the inflection points, not the curve shapes.

- Dead-neuron faults are genuinely graceful. Spyrou et al. (2021, hal-03036630) report an N-MNIST spiking

network losing no classification accuracy up to a 40% dead-neuron rate, and a DVS128 Gesture network holding above 80% accuracy at high dead-neuron rates.

- Saturated-neuron faults are not. SpikeFI (arXiv:2412.06795, 2024) establishes that saturated-neuron faults are

substantially more damaging than dead neurons. A neuron that fires constantly injects noise into every downstream computation.

- Stuck-at faults can be lethal at very low rates. ReSpawn and FalVolt report significant degradation in a systolic

SNN at stuck-at fault rates as low as 0.012%.

- Learning can partially substitute for redundancy. STDP-trained networks tolerate dead-neuron rates at or below

5% and synaptic bit-error rates at or below 10⁻² without MNIST accuracy impact (hal-05083335). The first actual neutron-beam test of a spiking network Nijsink et al. (University of Twente, arXiv:2605.00030, 2026) ran an ODIN spiking network on a PolarFire flash-FPGA under a neutron beam at ChipIR. Short exposures were stable. Two of six long runs of roughly four hours showed rapid accuracy collapse. The finding worth carrying forward is that enabling on-chip SDSP learning extended time-to-failure and partially recovered from bit-flips, which suggests online learning may substitute for some triple-modular-redundancy overhead. No single-event latch-ups were observed.

## DESIGN CONSEQUENCE

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 17 of 36 Protect against stuck-high, not against silence. The mitigation budget for a spiking inference payload should be weighted toward detecting and clamping saturated neurons and toward ECC and scrubbing on weight memory, rather than toward redundancy against neuron loss — which the architecture already absorbs.

### Hardening approaches and what each costs

## APPROACH WHAT IT ADDRESSES PENALTY

Radiation-hardening by process

## (RHBP)

TID and SEL at the device level. Limited part availability, older process nodes, high unit cost, long lead times. Radiation-hardening by design

## (RHBD)

SEU and SET on commercial processes. Area and power overhead, design complexity, requires foundry-specific expertise. Triple modular redundancy

## (TMR)

SEU and SET in logic. Triples area and power for the protected block. Rarely affordable across a whole inference engine — apply to the decision path only. ECC on weight memory SEU in stored parameters. Area overhead plus access latency. Cheap relative to TMR and usually the right first spend for an inference payload.

Memory scrubbing Accumulated SEU in configuration and weights. Continuous power and cycle cost. Necessary on SRAM-based FPGAs. COTS with mitigation Cost and capability, accepting risk. Viable for short LEO missions. Risk rises with altitude and duration. This is the Phi-sat and TechEdSat approach.

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- Use Case Deep Dives

Six deployment patterns, each with the architecture, the quantified benefit and an honest maturity assessment. The maturity assessments are collected in Exhibit 6 at the end of this section.

### On-board satellite intelligence — the strongest case

Maturity: TRL 8–9 for conventional CNNs. TRL 3–4 for spiking implementations. This is on-orbit image triage: cloud screening, change detection, ship and aircraft detection, wildfire and flood detection. It is the one application where the economics are already proven in flight.

ESA's Phi-sat-1, launched in 2020, ran the CloudScout convolutional network on an Intel Myriad 2 VPU at roughly 325 ms inference, about 92% accuracy and around 1% false-positive rate, drawing approximately 2 W per inference. Using this on-board cloud screening, the mission achieved a 90% reduction in downlink data volume (Reijonen et al., Aerospace 13(2):128, 2026). The flood-mapping fully convolutional mode delivered a further reduction of roughly one hundred fold in the data budget.

Comparable nanosatellite work using TriCloudNet with a pruned U-Net on a Zynq-7000, flown on the SNIPE mission, reports downlink volume reductions of 40 to 50%. Exhibit 3. The bits-to-decisions cascade. Every stage moved on-orbit is antenna time, ground egress and latency you no longer pay for. The final decision-product stage is an architectural projection, not a flight result.

The economics are simple to state. A hyperspectral instrument generates terabytes. If somewhere between half and seventy percent of scenes are cloud-obscured, on-board screening avoids downlinking them at all. Latency to decision drops from an orbit and a ground pass — tens of minutes to hours — down to seconds.

Where an event-driven front-end fits specifically is change and event detection, where only the delta matters: a wildfire flare-up, a new wake, a vehicle that was not there on the previous pass. That is a sparse problem, which is exactly the problem class where neuromorphic silicon earns its advantage.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 19 of 36

### Edge AI for LEO broadband user terminals

Maturity: design hypothesis. Not a documented deployment.

## SOURCING CAVEAT — READ BEFORE USING THIS SECTION

Per-terminal power figures for specific commercial LEO broadband terminals, including Starlink, could not be verified from primary sources during this research. No such figure is asserted here, and any downstream document that repeats one should cite a primary source or drop it.

What follows is an architecture argument, not a measurement. Consumer phased-array terminals are thermally and power constrained by construction. The machine learning problems they present are real and well-posed: beam management, interference mitigation and link adaptation are all optimisation problems with continuous, low-information-rate inputs and hard latency bounds.

That signal profile is a reasonable match for a sub-watt event-driven NPU. An Akida-class part at roughly 1 W, or an Innatera Pulsar at microwatt to milliwatt scale, could plausibly carry always-on link monitoring while the main SoC handles bursts. The case is architecturally coherent. It is not yet supported by a published deployment, and it should be treated as a prototype opportunity rather than a proven pattern.

### Autonomous satellite swarms and distributed constellations

Maturity: TRL 6–7 for the autonomy layer. NASA Ames' Distributed Spacecraft Autonomy experiment, flown on the four-CubeSat Starling mission from August 2023 to May 2024, achieved the first fully distributed autonomous operation of multiple spacecraft and the first use of space-to-space communications to autonomously share status information between multiple spacecraft. The swarm autonomously coordinated GPS channel selection to capture ionospheric events, including the Equatorial Ionization Anomaly and polar patches.

Starling 1.5 and later added torrent-style file chunking for data sharing across the swarm, plus autonomous collision avoidance. On the defence side the analogues are DARPA's Blackjack and Pit Boss programmes and the Space Development Agency Transport Layer.

The architectural elements that matter for an implementer are inter-satellite link budgets, split computing across nodes, and consensus under intermittent connectivity. Conflict-free replicated data types and gossip protocols are the right primitives here, because they converge without coordination when a partition heals. Event-driven, low-power inference maps cleanly onto always-on inter-satellite monitoring: each node needs to notice something worth telling its neighbours about, and noticing is cheap while reasoning is expensive.

### Low-power and intermittent-connectivity operation

Maturity: natural architectural fit. Deployable now. Small satellite power budgets are tight and cyclic. Orbit-average power scales with form factor: a 1U bus operates in the region of 1 to 2 W, a 3U at several watts, a 6U in the twenty-watt class, with 12U higher. Eclipse cycles impose roughly 35 minutes of darkness in a 90-minute low Earth orbit, which forces duty-cycling on any payload that cannot run off battery through the shadow.

Event-driven silicon maps onto this constraint almost too neatly. A part that draws dynamic power only on activity can stay powered through eclipse as a wake-on-event trigger while the main SoC sleeps. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 20 of 36 Exhibit 4. Orbit-average power as a function of burst duty cycle. The always-on front-end costs almost nothing. The gating is where the entire saving comes from.

The worked case: a 1 W always-on neuromorphic front-end gating a 10 W reasoning engine at a 1% duty cycle draws 1.0 plus 0.1, or 1.1 W orbit-average. That is an 89% reduction against running the reasoner continuously, and it retains continuous event coverage rather than sampling blind. A sub-milliwatt front-end makes the idle term effectively free.

The model above is a linear power budget. It excludes wake-transition energy and thermal soak, both of which favour longer and less frequent bursts than the arithmetic alone would suggest. Size the gate threshold accordingly.

### NASA and deep-space autonomy

Maturity: TRL 9 for the autonomy precedent. TRL 1–2 for neuromorphic implementations of it. Light-time delay is what makes on-board autonomy a requirement rather than an optimisation. Mars one-way light time ranges from roughly 4 to 24 minutes depending on orbital geometry, so a round-trip command cycle runs from about 8 to 48 minutes. Ground-in-the-loop tasking stops being operationally meaningful well before that.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 21 of 36 Exhibit 10. Round-trip light time by destination. Beyond roughly one minute, ground-in-the-loop tasking ceases to be an operational option and autonomy becomes a mission requirement.

The flight precedent is AEGIS, which has run on Curiosity since 2016 selecting ChemCam targets without ground involvement. Francis et al. (Science Robotics, 2017, doi:10.1126/scirobotics.aan4582) report that AEGIS autonomously selected the most desired target material with success exceeding 93%, against roughly 24% expected without intelligent targeting, and raised ChemCam yield from 256 to 327 observations per sol. It is implemented in 21,000 of Curiosity's 3.8 million lines of code. AEGIS now also targets SuperCam on Perseverance.

Two things follow for anyone designing a neuromorphic deep-space payload. First, autonomous science selection is a solved problem class with flight heritage, so the question is efficiency rather than feasibility. Second, AEGIS is 21,000 lines of deterministic code, which is a very different assurance argument from a stochastic spiking inference engine.

Section 7.4 returns to that.

### Defence applications

Maturity: mixed. The mission need is mature; the neuromorphic implementation is not. The applicable mission set includes missile warning and tracking, space domain awareness, resilient positioning navigation and timing, and on-orbit signals intelligence triage. Each has the same signature: high-rate sensor input, a small fraction of which is worth downlinking, under a latency requirement that a ground pass cannot meet.

Programme vehicles worth tracking are DIU, AFWERX, the Space Development Agency, and the relevant SBIR topics. AFRL awarded BrainChip a $1.8M neuromorphic radar contract in December 2024, which is the clearest current signal of defence interest in this specific part.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 22 of 36 Exhibit 6. Technology readiness across the capability set. The discontinuity between the top two rows and the bottom two rows is the entire commercial argument of this paper. A programme that budgets for the bottom rows and plans for the top rows will hold; one that budgets for the top rows will not.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 23 of 36

- Reference Architecture for Builders

This section is the deliverable for a solution engineer. It sets out where to draw the boundaries in a space-based event-driven inference node, and why each boundary sits where it does. Exhibit 5. Reference architecture for a space-based event-driven inference node. The always-on tier is event-driven and cheap. The reasoning tier is conventional, quantised and power-gated. Only the gate decides which events are worth waking for.

## THE SINGLE MOST IMPORTANT DESIGN DECISION

The neuromorphic tier is a filter, not the reasoner. Attempting to run autoregressive language generation on neuromorphic silicon is where current programmes fail, for the structural reasons set out in Section 4.2. Keep the spiking substrate on the detection problem it is genuinely good at, and gate a quantised conventional core for the language step.

### Spike encoding: choose deliberately

## SCHEME MECHANISM BANDWIDTH ACCURACY / LATENCY TRADE-OFF

Rate coding Information carried in firing frequency over a window. High spike count Robust and easy to train, but many timesteps means higher energy and latency. The default in conversion pipelines. Temporal / latency coding

## (TTFS)

Information carried in time-to-first-spike; at most one spike per neuron. Lowest Best sparsity, energy and latency. Harder to train and less robust to jitter. The ESA study found TTFS best across accuracy, latency, power and synaptic operations for classification.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 24 of 36

## SCHEME MECHANISM BANDWIDTH ACCURACY / LATENCY TRADE-OFF

Delta modulation Encode changes rather than absolute values. Proportional to scene change Native output format of event cameras. The right default when the sensor is a DVS or DAVIS. Graded spikes (Loihi 2) Spike carries an integer payload up to 24 bits.

Low Enables sigma-delta conversion. Brehove et al. achieved roughly 6% of the equivalent ANN's synaptic operations on YOLO-KP.

### Toolchain reality check

The gap between a working notebook and a flight payload is larger here than in conventional ML, because there is no portability layer. Every vendor SDK targets one silicon family.

## LAYER OPTIONS NOTE FOR IMPLEMENTERS

Training and simulation snnTorch, Norse, SpikingJelly, Nengo and NengoDL, Brian2 Norse was used in the ESA study. snnTorch and SpikingJelly have the most active ecosystems for surrogate-gradient training.

## Vendor deployment Intel Lava (Loihi), BrainChip MetaTF (Akida), SynSense

## Rockpool (Xylo, Speck), Innatera Talamo (Pulsar)

No portability between these. Choosing an SDK is choosing a silicon vendor for the life of the programme. Benchmarking NeuroBench algorithm track and system track Run this before believing any vendor ratio. It is the only community-accepted comparison framework.

Flight interfaces SpaceWire, SpaceFibre, CCSDS, CAN, MIL-STD-1553 None of the neuromorphic SDKs emit these. Budget integration effort explicitly. Packaging and deployment Hardened OCI container images where the bus supports it Container-based deployment simplifies reciprocity arguments where a programme has an existing accreditation path.

## WHAT FLIGHT DEPLOYMENT ACTUALLY REQUIRES BEYOND THE SDK

Radiation-tolerant packaging and part qualification, with test data you have seen rather than a partnership announcement. Thermal management — the TechEdSat-13 Loihi self-shut-down on runs beyond roughly 220 minutes and operated improperly below about 15 °C, which is a payload design constraint, not a footnote. Interface integration to SpaceWire, CCSDS or MIL-STD-1553. Software assurance evidence. Model update and signed-weight verification at load. None of this is in the vendor toolchain.

### Interfaces and standards

The relevant set is unchanged by the choice of accelerator: SpaceWire and SpaceFibre for high-rate on-board data, CCSDS for the downlink protocol stack, CAN and MIL-STD-1553 for command and control on buses that use them.

What changes is that no neuromorphic toolchain speaks any of them, so the integration layer is bespoke work that should be scoped at the start rather than discovered late.

### Verification, validation and the assurance gap

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 25 of 36 This is the least discussed and most likely to stop a programme. Testing a stochastic, event-driven inference system for a mission-critical application is an open problem. Spike timing is nondeterministic in ways that complicate reproducibility, surrogate-gradient training introduces its own nondeterminism, and there is no accepted certification path for the resulting artefact.

NASA-STD-8739.8 for software assurance, and the DO-178C analogues in the aviation domain, were written for deterministic code. AEGIS clears that bar because it is 21,000 lines of conventional software. A spiking inference engine does not, and no standardised neuromorphic-inference assurance or authorisation framework currently exists.

## THE GOVERNANCE GAP IS THE REAL BLOCKER

For crewed missions and high-value assets, the absence of a certification path for stochastic inference is a harder constraint than either the energy budget or the radiation environment. Those two are engineering problems with known mitigations. This one requires a standards body to move.

The practical mitigation available today is architectural: keep the stochastic component inside a bounded, monitored envelope, put the deterministic decision logic downstream of it, and instrument the boundary so that the assurance argument applies to the system rather than to the model. That is the same control-plane pattern that makes governed AI deployable in regulated commercial environments, and it transfers directly.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 26 of 36

- Economics and Mission Trade-offs

### Downlink economics

AWS Ground Station bills per minute of antenna time, tiered by narrowband below 40 MHz versus wideband at or above 40 MHz, and by on-demand versus reserved, where reserved pricing requires a twelve-month commitment. A dedicated antenna site costs in the region of one to five million dollars to build, plus staffing. Below a few hundred contacts per month, ground-station-as-a-service is the cheaper option.

The value of on-board triage follows directly. Every scene discarded on-orbit is antenna time not booked, ground egress not paid for, and processing not performed. At the 90% reduction demonstrated by Phi-sat-1, ground segment cost scales down close to proportionally.

### Compute-in-orbit versus downlink-and-process

## FAVOURS ON-BOARD COMPUTE FAVOURS DOWNLINK-AND-PROCESS

Data generated substantially exceeds downlink capacity Raw data has archival or scientific value beyond the immediate decision Latency to decision matters — defence, disaster response, tip-and-cue Models change frequently and retraining cadence is high The decision, not the data, is the product Ground compute is effectively free relative to the mission budget Connectivity is contested, intermittent or policy-restricted Regulatory or scientific requirements mandate raw data retention Phi-sat's approach is the pragmatic middle path and worth copying: downlink a small sample of raw imagery for ground retraining, uplink the updated model, and let the on-board system handle the remaining volume. It preserves the ability to improve the model without preserving the cost of moving everything.

### Power, mass and dollars

Watts saved translate through a chain that ends in launch cost. Less continuous processing power means smaller solar array area and less battery mass, which means less spacecraft mass. On a small satellite with an orbit-average budget in the twenty-watt class, a front-end that removes ten to sixty watts of continuous processing draw changes the array sizing rather than trimming a margin.

### Orbital data centres, and where edge inference sits relative to them

Starcloud launched Starcloud-1 on 2 November 2025, a roughly 60 kg satellite carrying the first NVIDIA H100 in orbit at about 325 km on an eleven-month mission. In December 2025 it ran Google's Gemma model and trained NanoGPT on orbit. Google's Project Suncatcher, Aetherflux, and Aethero — which flew the first NVIDIA Jetson in space in 2025 — are peer efforts.

Starcloud's stated future 5 GW data centre with an approximately 4 km² solar array is a forecast, and is labelled as such. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 27 of 36 These are complementary to, not competitive with, the architecture in Section 7. Orbital data centres target heavy training and inference on data that is already in space. Neuromorphic edge nodes target always-on, per-sensor triage in the microwatt-to-watt envelope on platforms that will never carry an H100. A constellation may reasonably want both, with the edge nodes deciding what is worth sending to the orbital compute node.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 28 of 36

- Limitations and Honest Assessment

Every technical case is more useful when it states where it fails. These are the conditions under which the argument in this paper does not hold.

## LIMITATION CURRENT STATE

Accuracy gap in language Vision SNNs are within a few percentage points of conventional networks on ImageNet top-1. Spiking language models lag conventional models and mostly demonstrate the method rather than deployable quality.

Tooling immaturity Each vendor ships a proprietary SDK with no portability between them. Flight toolchains barely exist. Choosing an SDK commits the programme to a silicon vendor. Absent flight heritage for language models None. Loihi 1 on TechEdSat-13 is a technology demonstration, not an operational payload, and it ran no language workload.

Training difficulty Surrogate gradients, backpropagation-through-time memory cost, and no standard training recipe that transfers across problem classes. Benchmark immaturity NeuroBench is new as of 2025 and adoption is still in progress. Before it, cross-architecture comparison was effectively unregulated.

Radiation data gap One paywalled ground-test paper on Loihi. No public quantitative test data on Akida. The evidence base is thinner than the commercial activity suggests. Certification path None exists for stochastic, event-driven inference in mission-critical software. This is a standards-body problem, not an engineering one.

### The overpromising risk, stated directly

This field has a two-decade history of announcing capability ahead of deployment. TrueNorth was announced in 2014 with a great deal of attention and saw limited operational use. The framing that invites the same outcome now is the thousand-fold efficiency claim and the brain-scale comparison, both of which set an expectation that the deployed systems will not meet.

The honest position is narrower and more durable. Event-driven computation delivers a real, measurable, order-of-magnitude advantage on sparse problems, on specific parts, against specific baselines. That is a good enough result to build on. It does not need inflating, and inflating it is what produces the funding cycles this field keeps living through.

### What would change the assessment

Four developments would move items in Exhibit 11 up a stage. They are stated as falsifiable conditions so that a programme can watch for them rather than re-litigate the question annually.

- A spiking language model demonstrated natively on neuromorphic silicon at accuracy competitive with a

quantised conventional model of similar capability.

- Published TID at or above 30 krad(Si) with demonstrated SEL immunity on a neuromorphic accelerator, from

an independent test facility rather than a vendor announcement. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 29 of 36

- A NeuroBench system-track result showing a greater than 10× energy advantage against a current edge GPU —

not a desktop or server part — on a workload representative of yours.

- A defensible certification path for stochastic inference in mission-critical software, whether through NASA, a

DO-178C analogue, or an equivalent standards route. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 30 of 36

- What to Build, What to Pilot, What to Leave Alone

The staging below is the operational conclusion of this document. Exhibit 11. Three-stage adoption model with the signals that would justify promoting an item between stages.

### Stage 1 — build now (0 to 12 months)

- On-board triage and change detection: deploy a quantised CNN on a COTS VPU or FPGA of the Myriad or Zynq

class. This is TRL 8 to 9 with Phi-sat flight heritage. It is the lowest-risk path to a real capability.

- Always-on event detection in the microwatt-to-watt envelope: prototype on BrainChip Akida with MetaTF, or

Innatera Pulsar with Talamo, fed by an event-camera front-end.

- Any language or reasoning requirement: use an extreme-quantised BitNet b1.58 ternary model on conventional

edge silicon. Deployable today, no neuromorphic dependency.

- Architecture: adopt the hybrid always-on plus power-gated-burst pattern from Section 7 and compute the

duty-cycle power budget explicitly rather than assuming it.

### Stage 2 — pilot (12 to 36 months)

- Benchmark before believing: run the NeuroBench algorithm and system tracks on your actual workload before

accepting any vendor efficiency ratio as a design input.

- Engage the rad-hard neuromorphic path: track Frontgrade Gaisler's GR801 and GRAIN SoC as it qualifies, and

demand real TID and SEE test data before design-in. A partnership announcement is not test data.

- Fund fault-injection V&V: target saturated-neuron and stuck-at faults specifically. Dead-neuron testing alone

will produce a falsely reassuring result, for the reasons in Section 5.3. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 31 of 36

### Stage 3 — watch, do not build (36 months and beyond)

- Spiking language models executing natively on neuromorphic silicon at competitive accuracy.
- Billion-parameter spiking models with an on-chip demonstration.
- A standardised assurance framework for stochastic, event-driven inference in flight software.

### Where Enclavia fits

Enclavia.ai builds the governance and control-plane layer for agentic AI in regulated and sovereignty-bound environments. The connection to this paper is Section 7.4. The engineering problems in space-based edge intelligence — power, radiation, sparsity — have known mitigations and a clear research trajectory. The problem that does not is the assurance argument: how you authorise a stochastic inference system to operate inside a mission-critical boundary, produce evidence that it behaved as specified, and detect when it stops. That is a control-plane problem, and it is the same one that blocks regulated commercial deployment.

The architectural answer is consistent across both domains. Keep the stochastic component inside a bounded, instrumented envelope. Put deterministic decision logic downstream of it. Monitor for drift and hallucination continuously rather than in post-hoc review. Emit signed evidence as the system runs rather than assembling it afterward. Whether the boundary is a spacecraft trust boundary or a clinical data boundary, the control plane is the same shape.

If you are scoping a programme in this area and want to compare notes on the assurance layer specifically, the contact details are on the cover. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 32 of 36

## Appendix A. Evidence Ledger

A.1 Tier 1 — independently benchmarked, peer-reviewed or flight-validated

- Loihi 2 keyword-spotting benchmark: up to 250× less energy and 18× faster than an NVIDIA Jetson Orin Nano

(Spiking Heidelberg Digits, batch size 1).

- Phi-sat-1 CloudScout: ~325 ms inference, ~92% accuracy, ~1% false positive, ~2 W per inference, ~90% downlink

data reduction.

- Falcon Neuro DAVIS 240C on ISS: of 18 degradation measures tracked over January 2022 to September 2024,

only one showed a convincing deterioration trend at 99% confidence. No SEL or single-event burnout observed.

- AEGIS on Curiosity: autonomous target selection success exceeding 93% against a ~24% no-intelligence

baseline; ChemCam yield raised from 256 to 327 observations per sol; 21,000 of 3.8 million lines of code.

- NASA Starling DSA: first fully distributed autonomous operation of multiple spacecraft; first use of

space-to-space communications for autonomous status sharing.

- Meta-SpikeFormer / Spike-driven Transformer V2: 80.0% ImageNet-1K top-1 at 55M parameters. V3: 86.2% at

173M. QSD-Transformer: 80.3% at 6.8M parameters and 8.7 mJ.

- Spike-driven Transformer SDSA: up to 87.2× lower attention-computation energy than vanilla self-attention.
- BitNet b1.58: matches full-precision LLaMA perplexity at 3B parameters while running 2.71× faster with 3.55× less

GPU memory; at 70B, 8.9× higher throughput and 71.4× more energy-efficient matrix multiplication.

- SpikeLLM on LLaMA-7B W4A4: WikiText2 perplexity reduced 11.01% and reasoning accuracy improved 2.55%

against OmniQuant.

- NSLLM 1.5B on VCK190 FPGA: 13.849 W dynamic power, 161.8 tokens per second, 19.8× / 21.3× / 2.2× improvements

in energy, memory and throughput against an A800 GPU.

- SNN fault injection: no N-MNIST accuracy loss to a 40% dead-neuron rate; DVS128 Gesture above 80% at high

dead-neuron rates; stuck-at degradation from ~0.012%; STDP tolerance at ≤5% dead neurons and ≤10⁻² synaptic BER.

- IBM TrueNorth: 4,096 cores, 1M neurons, 256M synapses, 65 mW real-time, 400 GSOPS/W. NorthPole: 25× more

frames per joule than a 12 nm GPU on ResNet-50.

- Sigma-delta conversion on Loihi 2: roughly 6% of the equivalent ANN's synaptic operations on YOLO-KP.

A.2 Tier 2 — vendor-stated or press-reported

- Intel Hala Point: 100× less energy and 50× faster than CPU/GPU on selected workloads; greater than 15 TOPS/W;

20 petaops.

- IBM NorthPole LLM latency claims: sub-millisecond per token on a 3B model, 70× more energy-efficient than the

next-lowest-latency GPU.

- Innatera Pulsar: 500× lower energy and 100× lower latency than a conventional AI microcontroller; 600 μW radar

presence detection; 400 μW audio scene classification.

- Starcloud on-orbit milestones: Starcloud-1 launched 2 November 2025 with the first NVIDIA H100 in orbit; ran

Google Gemma and trained NanoGPT in December 2025. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 33 of 36 A.3 Tier 3 — forecast, projection or conditional

- Starcloud's 5 GW future data centre with an approximately 4 km² solar array.
- Any timeline for a neuromorphic language model operating in orbit.
- Edge NPU workloads on commercial LEO user terminals, including the argument in Section 6.2.

A.4 Excluded — could not be verified from a primary source

## NOT ASSERTED ANYWHERE IN THIS DOCUMENT

- Exact TID and SEE cross-section figures for Intel Loihi. The dedicated ground-test paper (Scrofano, Davis and

Taggart, 2024 IEEE Space Computing Conference, pp. 86–92) is paywalled and the values could not be read from a primary source.

- Any TID or SEE test data for BrainChip Akida. None exists publicly. Vendor partnership announcements, including

the Frontgrade Gaisler IP licensing, are not test data.

- Power budgets for specific commercial LEO user terminals, including Starlink.
- A Loihi-2-specific picojoule-per-synaptic-operation figure. The widely circulated 23.6 pJ value is a Loihi 1 number

from Davies et al. (2018). Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 34 of 36

## Appendix B. Primary Sources

Prioritised toward 2024 to 2026 for state of the art, with foundational earlier work retained where it remains canonical. B.1 Neuromorphic computing and benchmarking

- Mészáros, L. et al. Loihi 2 benchmarking against edge GPU baselines. arXiv:2510.13757 (October 2025).
- NeuroBench: a framework for benchmarking neuromorphic computing algorithms and systems. Nature

Communications (2025). DOI 10.1038/s41467-025-56739-4.

- Davies, M. et al. Loihi: a neuromorphic manycore processor with on-chip learning. IEEE Micro (2018). Source of

the 23.6 pJ per synaptic operation figure, which applies to Loihi 1.

- Intel Newsroom. Hala Point system specifications (April 2024).
- IBM Research. NorthPole architecture and benchmarks. Science (2023).
- Lunghi, P. et al. (ESA / Politecnico di Milano). Spiking neural networks for space applications. arXiv:2505.11418

(2025).

- Brehove, S. et al. Sigma-delta neural network conversion on Loihi 2. arXiv:2505.06417 (2025).
- NEXUS. arXiv:2601.21279.
- Akida energy characterisation. arXiv:2603.13880 and arXiv:2507.15958.

B.2 Spiking and quantised language models

- Zhu, R.-J. et al. SpikeGPT: generative pre-trained language model with spiking neural networks.

arXiv:2302.13939.

- Xing, X. et al. SpikeLLM: scaling up spiking neural networks to large language models via saliency-based spiking.

arXiv:2407.04752. ICLR 2025.

- Spike-driven Transformer. NeurIPS 2023.
- Meta-SpikeFormer / Spike-driven Transformer V2. ICLR 2024.
- Scaling spike-driven transformer with efficient spike firing approximation training (V3). IEEE T-PAMI 2025.
- Quantized Spike-driven Transformer (QSD-Transformer). ICLR 2025. arXiv:2501.13492.
- Neuromorphic spike-based large language model (NSLLM). PMC12906346.
- Ma, S. et al. The era of 1-bit LLMs: all large language models are in 1.58 bits. arXiv:2402.17764.

B.3 Radiation effects and space environment

- Scrofano, R., Davis, J. and Taggart, J. (The Aerospace Corporation). Radiation testing of the Intel Loihi

neuromorphic processor. 2024 IEEE Space Computing Conference, pp. 86–92.

- Murbach, M. et al. TechEdSat-13 / BrainStack. SSC23-X-03. NASA NTRS 20230011460.
- Wilcox, S. et al. Long-duration performance assessment of event-based sensors on the International Space

Station. Sensors 25(21):6599 (2025). DOI 10.3390/s25216599. Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 35 of 36

- Nijsink, T. et al. (University of Twente). Neutron-beam radiation testing of a spiking neural network on a flash

FPGA. arXiv:2605.00030 (2026).

- Spyrou, T. et al. Neuron fault tolerance in spiking neural networks. hal-03036630 (2021).
- SpikeFI: a fault injection framework for spiking neural networks. arXiv:2412.06795 (2024).
- STDP fault tolerance characterisation. hal-05083335.
- ReSpawn and FalVolt fault-tolerance studies for systolic SNN accelerators.

B.4 Space missions and on-board autonomy

- Reijonen, J. et al. On-board AI for Earth observation. Aerospace 13(2):128 (2026). Source for the Phi-sat-1 90%

downlink reduction figure.

- Francis, R. et al. AEGIS autonomous targeting for ChemCam on Mars Science Laboratory. Science Robotics

(2017). DOI 10.1126/scirobotics.aan4582.

- NASA Ames. Starling and Distributed Spacecraft Autonomy mission results (2023–2024). nasa.gov.
- On-orbit AI: cloud detection for resource-limited nanosatellites. International Journal of Aeronautical and Space

Sciences (2024). DOI 10.1007/s42405-024-00865-8.

- Frontgrade Gaisler. GR801 / GRAIN rad-hard SoC with BrainChip Akida IP (December 2024).

B.5 Economics and orbital infrastructure

- AWS Ground Station pricing. aws.amazon.com/ground-station/pricing.
- Starcloud-1 launch and on-orbit H100 operation. Data Center Dynamics, CNBC and Space.com

(November–December 2025).

## Enclavia.ai · Sovereign Agentic AI for Regulated and Contested Environments

## Your Data · Your AI · Your Way

Dev Roy, Founder & CEO · dev@enclavia.ai · 703-984-9981 · enclavia.ai · Fairfax, Virginia This document is a technical assessment prepared for engineering audiences. Figures carry the evidence tier under which they were sourced. Claims that could not be verified from a primary source are named in Appendix A.4 and are not asserted in the body text. Readers are encouraged to check the primary sources in Appendix B directly rather than relying on this summary.

Your Data · Your AI · Your Wayv1.0 · 31 July 2026 · Page 36 of 36